1. Field of the Invention
This invention relates to a PLL (Phase Locked Loop) circuit and, in particular, to the PLL circuit that enables adjustment of frequency of the signals outputted corresponding to external signals and at the same time permits output of a high-accuracy clock having high phase accuracy in reference to an ideal clock.
2. Description of Related Art
In recent years, an optical disk device which can record or reproduce data in or from CDs, DVDs, and other optical disks has become popular. The optical disk media have wobble with a certain cycle engraved in the grooves formed on the disk surface. In the optical disk device, the wobble signal created on the basis of this wobble is given to the PLL circuit to generate a synchronous clock signal used at the time of recording and reproduction. For this purpose, the optical disk device is mounted with the PLL circuit which varies the frequency of the clock in accordance with the wobble. In order to carry out recording or reproducing of data in or from the optical disks with accuracy, the PLL circuit mounted on the optical disk device is required to ensure high phase accuracy in generating a clock signal synchronized with the clock signal of originating synchronous source determined by the wobble signal.
Examples of the PLL circuit that creates a clock signal synchronized with the reference signal with a high accuracy are disclosed in the patent document 1 and 2 (to be referred to hereafter as “the Patent Document 1” and “the Patent Document 2” respectively). The PLL circuits disclosed in the Patent Document 1 and the Patent Document 2 are able to create a clock synchronized with the reference signal with a high accuracy, but cannot alter the range of frequency variance of the clock signal to be created. In the case of the optical disk media, there is a large difference in distance between the inner circumferences, and the outer circumferences, and therefore, between reading in the inner circumference side and reading in the outer circumference side, the frequency of the wobble signal is varied more than twice between the inner side and the outer side. For this reason, the PLL circuit mounted on the optical device needs to vary the frequency of the clock signal to be created over a range twice as wide from the low side to the high side according to the wobble signal. Accordingly, the PLL circuits disclosed in the Patent Document 1 and the Patent Document 2 have a problem in that these circuits cannot be used for the purpose that requires such a wide-ranged frequency variance.
Contrary to the above, the PLL circuit disclosed in the patent document 3 (to be referred to hereafter as “the Patent Document 3” ) is able to create a high-accuracy clock synchronized with the reference clock with sufficient accuracy, while varying the frequency of the clock signal created according to the value of the frequency control input to be given from the external source. Shown in FIG. 7 is a block diagram of the PLL circuit 100 disclosed in the Patent Document 3. As shown in FIG. 7, the PLL circuit 100 includes the digital VCO 101 and the delay line 102. The digital VCO 101 performs control of the frequency of the output clock in accordance with the frequency control input and outputting of the data (e.g., delay amount data) about phase difference from the reference signal, the originating synchronous source for the output clock. The delay line 102 outputs the high-accuracy clock by delaying the rising edge of the output clock in accordance with the data of delay amount.    [Patent Document 1] Japanese Patent Laid-Open Application No. 2001-510955    [Patent Document 2] Japanese Patent Laid-Open Application No. 2002-100965    [Patent Document 3] Japanese Patent Laid-Open Application No. 2005-191831
The Patent Document 3 uses the DLL (Delay-Locked Loop) for the delay line 102. Generally this DLL is large in circuit scale and power consumption. Due to such features, a semiconductor device mounted with the PLL circuit 100 of the Patent Document 3 has problems in that the chip size becomes large and the power consumption of the device also increases.